A LOW POWER VERNIER TIME-TO-DIGITAL CONVERTER USING ADIABATIC LOGIC

被引：0

作者：

Mahima, R. ^{[1
]}

Muralidharan, D. ^{[2
]}

机构：

[1] SASTRA Univ, Sch Comp, VLSI Design, Thanjavur, Tamil Nadu, India

[2] SASTRA Univ, Sch Comp, Thanjavur, Tamil Nadu, India

来源：

2017 INTERNATIONAL CONFERENCE ON NETWORKS & ADVANCES IN COMPUTATIONAL TECHNOLOGIES (NETACT) | 2017年

关键词：

Time-to-Digital Converter (TDC); Vernier Time-to-Digital Converter (VTDC); All-Digital Phase Locked Loop (ADPLL); Digital Phase Locked Loop (DPLL); Delay Locked Loop (DLL);

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, an adiabatic based vernier time-to-digital converter (VTDC) is proposed. Generally, static based vernier TDC consumes more power due to two delay chain and D-flipflop. To avoid this issue an adiabatic based vernier TDC is proposed. This proposed TDC is constructed by using adiabatic inverter and D-flipflop but in classical TDC architecture consists of static based inverter and D-flipflop. A high resolution with low power is achieved in proposed TDC. Here, 2 stages, 3 stages, 4 stages traditional and proposed vernier TDC are implemented and also discussed about power consumption comparison of 2 stages, 3 stages, 4 stages conventional and proposed vernier TDC at different supply voltages. This vernier TDC is simulated in 180nm CMOS technology. Its operating frequency is 1.5KHZ.

引用

页码：90 / 94

页数：5

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