A LOW-POWER CMOS TIME-TO-DIGITAL CONVERTER

被引：86
|
作者：
RAISANENRUOTSALAINEN, E
RAHKONEN, T
KOSTAMOVAARA, J
机构：
[1] Department of Electrical Engineering, University of Oulu
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 09期
关键词：
D O I：
10.1109/4.406397
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A time-to-digital converter, TDC, with 780 ps Isb and 10-mu s input range has been integrated in a 1.2-mu m CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5 +/- 0.5 V, and the operating temperature range is -40 to + 60 degrees C. Single-shot accuracy is 3 ns and accuracy after averaging is +/- 120 ps with input time intervals 5-500 ns. In the total input range of 10 mu s, the final accuracy after averaging is +/- 200 ps, Current consumption is 3 mA, and the chip size is 2.9 mm * 2.5 mm.
引用
收藏
页码：984 / 990
页数：7
相关论文
共 50 条
  • [1] Low-power CMOS time-to-digital converter
    Univ of Oulu, Oulu, Finland
    [J]. IEEE J Solid State Circuits, 9 (984-990):
  • [2] A low-cost low-power CMOS time-to-digital converter based on pulse stretching
    Chen, Poki
    Chen, Chun-Chi
    Shen, You-g Shen
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (04) : 2215 - 2220
  • [3] A low power high accuracy CMOS time-to-digital converter
    Chen, PK
    Liu, SI
    Wu, JS
    [J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 281 - 284
  • [4] A Low-Power Time-to-Digital Converter for Sensor Interface Circuits
    Rostami, Mohammad Saleh
    Saberi, Mehdi
    Maymandi-Nejad, Mohammad
    Sawan, Mohamad
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (12) : 2853 - 2857
  • [5] A Low-Power Coarse-Fine Time-to-Digital Converter in 65nm CMOS
    Zhang, Xue-Jiao
    Cui, Ke-Ji
    Zou, Zhuo
    Zheng, Li-Rong
    [J]. 2015 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS), 2015,
  • [6] Low-power, latch-based multistage time-to-digital converter in 65nm CMOS technology
    Razmdideh, Ramin
    Saneei, Mohsen
    [J]. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2018, 46 (06) : 1264 - 1271
  • [7] A Low-power Synthesizable Time-to-Digital Converter using Amplification to Overcome Mismatch
    Lin, Cong
    Wang, Bo
    Zhang, Chen
    Qi, Xingyu
    [J]. 2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2020, : 794 - 797
  • [8] Design of an All-Digital, Low Power Time-to-Digital Converter in 0.18μm CMOS
    Pokhara, Ankur
    Agrawal, Jatin
    Mishra, Biswajit
    [J]. 2017 7TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED), 2017,
  • [9] A REVIEW OF CMOS TIME-TO-DIGITAL CONVERTER
    Wang, Zixuan
    Huang, Cheng
    Wu, Jianhui
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2014, 23 (07)
  • [10] Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption
    Chen, PK
    Liu, SI
    Wu, JH
    [J]. ELECTRONICS LETTERS, 1997, 33 (10) : 858 - 860
12345