Optical multi-token-ring networking using smart pixels with field programmable gate arrays (FPGAs)

被引:0
|
作者
Zhang, LP [1 ]
Hong, SW [1 ]
Min, CK [1 ]
Alpaslan, ZY [1 ]
Sawchuk, AA [1 ]
机构
[1] Univ So Calif, Inst Signal & Image Proc, Los Angeles, CA 90089 USA
关键词
optical interconnections; optical computing; smart pixels; optoelectronic integrated circuits; vertical-cavity surface-emitting lasers;
D O I
10.1117/12.449653
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the implementation of an optical multi-token-ring network testbed system. Monolithic smart pixel CMOS OEICs are of paramount importance to high performance networks, communication switches, computer interfaces, and parallel signal processing for demanding future multimedia applications. The general testbed system is called Reconfigurable Translucent Smart Pixel Array (R-Transpar) and includes a field programmable gate array (FPGA), a transimpedance receiver array, and an optoelectronic very large-scale integrated (OE-VLSI) smart pixel array. The FPGA is an Altera FLEX10K100E chip that performs logic functions and receives inputs from the transimpedance receiver array. A monolithic (OE-VLSI) smart pixel device containing an array of 4 x 4 vertical-cavity surface-emitting lasers (VCSELs) spatially interlaced with an array of 4 x 4 metal-semiconductor-metal (MSM) detectors connects to these devices and performs optical input-output functions. These components are mounted on a printed circuit board for testing and evaluation of integrated monolithic OEIC designs and various optical interconnection techniques. The system moves information between nodes by transferring 3-D optical packets in free space or through fiber image guides. The R-Transpar system is reconfigurable to test different network protocols and signal processing functions. In its operation as a 3-D multi-token-ring network, we use a specific version of the system called Transpar-Token-Ring (Transpar-TR) that uses novel time-division multiplexed (TDM) network node addressing to enhance channel utilization and throughput. Host computers interface with the system via a high-speed digital I/O board that sends commands for networking and application algorithm operations. We describe the system operation and experimental results in detail.
引用
收藏
页码:146 / 154
页数:9
相关论文
共 50 条
  • [22] A multi-terminal net router for field-programmable gate arrays
    Bhatia, D
    Chowdhary, A
    VLSI DESIGN, 1996, 4 (01) : 1 - 10
  • [23] Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays
    Smekal, David
    Frolka, Jakub
    Hajny, Jan
    IFAC PAPERSONLINE, 2016, 49 (25): : 384 - 389
  • [24] Intrinsic Evolution of Analog Circuits Using Field Programmable Gate Arrays
    Whitley, Derek
    Yoder, Jason
    Carpenter, Nicklas
    ARTIFICIAL LIFE, 2022, 28 (04) : 499 - 516
  • [25] Frequency Synchronization for Wireless Networks using Field Programmable Gate Arrays
    Appel, Markus
    Wermke, Felix
    Winkler, Frank
    Meffert, Beate
    23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 2016, : 460 - 463
  • [26] Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays
    Bogdan, Istvan A.
    Coca, Daniel
    Beynon, Rob J.
    IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2009, 3 (03) : 142 - 149
  • [27] Introduction to embedded system design using field programmable gate arrays
    Simpkins, Alex
    IEEE Robotics and Automation Magazine, 2013, 20 (04): : 163 - 164
  • [28] Configuration and debug of field programmable gate arrays using MATLAB®/SIMULINK®
    Grout, I
    Ryan, J
    O'Shea, T
    Sensors & Their Applications XIII, 2005, 15 : 244 - 249
  • [29] Total dose responses of Actel 1020B and 1280A field programmable gate arrays (FPGAs)
    Katz, R
    Swift, G
    Shaw, D
    RADECS 95 - THIRD EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS, 1996, : 412 - 419
  • [30] Smart move: A placement-aware retiming and replication method for field programmable gate arrays
    Suaris, P
    Wang, DS
    Chou, NC
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 67 - 70