Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

被引：8

作者：

Smekal, David ^{[1
]}

Frolka, Jakub ^{[1
]}

Hajny, Jan ^{[1
]}

机构：

[1] Brno Univ Technol, Fac Elect Engn & Commun, Tech 12, Brno, Czech Republic

来源：

IFAC PAPERSONLINE | 2016年 / 49卷 / 25期

关键词：

AES; FPGA; VHDL; implementation; encryption; decryption; netCOPE; MONTGOMERY MODULAR EXPONENTIATION;

D O I：

10.1016/j.ifacol.2016.12.075

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

引用

页码：384 / 389

页数：6

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