Optical multi-token-ring networking using smart pixels with field programmable gate arrays (FPGAs)

被引:0
|
作者
Zhang, LP [1 ]
Hong, SW [1 ]
Min, CK [1 ]
Alpaslan, ZY [1 ]
Sawchuk, AA [1 ]
机构
[1] Univ So Calif, Inst Signal & Image Proc, Los Angeles, CA 90089 USA
关键词
optical interconnections; optical computing; smart pixels; optoelectronic integrated circuits; vertical-cavity surface-emitting lasers;
D O I
10.1117/12.449653
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the implementation of an optical multi-token-ring network testbed system. Monolithic smart pixel CMOS OEICs are of paramount importance to high performance networks, communication switches, computer interfaces, and parallel signal processing for demanding future multimedia applications. The general testbed system is called Reconfigurable Translucent Smart Pixel Array (R-Transpar) and includes a field programmable gate array (FPGA), a transimpedance receiver array, and an optoelectronic very large-scale integrated (OE-VLSI) smart pixel array. The FPGA is an Altera FLEX10K100E chip that performs logic functions and receives inputs from the transimpedance receiver array. A monolithic (OE-VLSI) smart pixel device containing an array of 4 x 4 vertical-cavity surface-emitting lasers (VCSELs) spatially interlaced with an array of 4 x 4 metal-semiconductor-metal (MSM) detectors connects to these devices and performs optical input-output functions. These components are mounted on a printed circuit board for testing and evaluation of integrated monolithic OEIC designs and various optical interconnection techniques. The system moves information between nodes by transferring 3-D optical packets in free space or through fiber image guides. The R-Transpar system is reconfigurable to test different network protocols and signal processing functions. In its operation as a 3-D multi-token-ring network, we use a specific version of the system called Transpar-Token-Ring (Transpar-TR) that uses novel time-division multiplexed (TDM) network node addressing to enhance channel utilization and throughput. Host computers interface with the system via a high-speed digital I/O board that sends commands for networking and application algorithm operations. We describe the system operation and experimental results in detail.
引用
收藏
页码:146 / 154
页数:9
相关论文
共 50 条
  • [31] Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays
    Tufa G.T.
    Andargie F.A.
    Bijalwan A.
    Computational Intelligence and Neuroscience, 2022, 2022
  • [32] Multiple curve presentation and zooming processor using Field Programmable Gate Arrays
    Venkatesan, Dhushyanth
    Elkeelany, Omar
    IEEE SOUTHEASTCON 2011: BUILDING GLOBAL ENGINEERS, 2011, : 105 - 110
  • [33] A hardware implementation of artificial neural networks using field programmable gate arrays
    Won, E.
    NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2007, 581 (03): : 816 - 820
  • [34] Upgrading Obsolete Integrated Circuits using Field Programmable Gate Arrays (FPGA)
    Thompson, Conchetta
    2014 IEEE AUTOTESTCON, 2014,
  • [35] Distributed arithmetic implementation of multivariable controllers using Field Programmable Gate Arrays
    Yuan, LF
    Sana, S
    Pottinger, HJ
    Rao, VS
    SMART STRUCTURES AND MATERIALS 1999: SMART ELECTRONICS AND MEMS, 1999, 3673 : 249 - 260
  • [36] Synchronization in coupled Ikeda delay systemsExperimental observations using Field Programmable Gate Arrays
    D. Valli
    B. Muthuswamy
    S. Banerjee
    M.R.K. Ariffin
    A.W.A. Wahab
    K. Ganesan
    C.K. Subramaniam
    J. Kurths
    The European Physical Journal Special Topics, 2014, 223 : 1465 - 1479
  • [37] Using field programmable gate arrays to scale up the speed of holographic video computation
    Nwodoh, TA
    JOURNAL OF ELECTRONIC IMAGING, 2003, 12 (03) : 558 - 566
  • [38] Real-time sound localization using field-programmable gate arrays
    Nguyen, D
    Aarabi, P
    Sheikholeslami, A
    2003 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL II, PROCEEDINGS: SPEECH II; INDUSTRY TECHNOLOGY TRACKS; DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS; NEURAL NETWORKS FOR SIGNAL PROCESSING, 2003, : 573 - 576
  • [39] Real-time sound localization using field-programmable gate arrays
    Nguyen, D
    Aarabi, P
    Sheikholeslami, A
    2003 INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOL II, PROCEEDINGS, 2003, : 829 - 832
  • [40] CREATING UNIQUE IDENTIFIERS ON FIELD PROGRAMMABLE GATE ARRAYS USING NATURAL PROCESSING VARIATIONS
    Crouch, James W.
    Patel, Hiren J.
    Kim, Yong C.
    Bennington, Robert W.
    2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 578 - +