Thermal-aware mapping and placement for 3-D NoC designs

Networks on Chip (NoC) and 3-D Integrated Circuits have been proposed as solutions to the ever-growing interconnect woes surrounding Systems-On-Chip. 3-D designs however suffer from hotspot creation, due to the increase in the power density of parts of the chip. In this paper, we propose the use of a genetic algorithm for a thermal and communication aware mapping and placement of application tasks on 3-D NoC environment. Our results show a significant reduction in system temperature when compared to a random mapping and placement, and provide an encouraging situation for migration to the 3-D design space.