Thermal-aware mapping and placement for 3-D NoC designs

被引：0
|
作者：
Addo-Quaye, C [1 ]
机构：
[1] Penn State Univ, University Pk, PA 16802 USA
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Networks on Chip (NoC) and 3-D Integrated Circuits have been proposed as solutions to the ever-growing interconnect woes surrounding Systems-On-Chip. 3-D designs however suffer from hotspot creation, due to the increase in the power density of parts of the chip. In this paper, we propose the use of a genetic algorithm for a thermal and communication aware mapping and placement of application tasks on 3-D NoC environment. Our results show a significant reduction in system temperature when compared to a random mapping and placement, and provide an encouraging situation for migration to the 3-D design space.
引用
收藏
页码：25 / 28
页数：4
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