Limited switch dynamic logic circuits for high-speed low-power circuit design

被引：6
|
作者：
Belluomini, W
Jamsek, D
Martin, AK
McDowell, C
Montoye, RK
Ngo, HC
Sawada, J
机构：
[1] IBM Corp, Almaden Res Ctr, Div Res, San Jose, CA 95120 USA
[2] IBM Corp, Div Res, Austin Res Lab, Austin, TX 78758 USA
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2006年 / 50卷 / 2-3期
关键词：
D O I：
10.1147/rd.502.0277
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a new circuit family-limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130-nm technology and one in 90-nm technology. The 130- and 90-nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.
引用
收藏
页码：277 / 286
页数：10
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