Quality Evaluation of Digital Soft IP Core for FPGA System

被引:0
|
作者
Lei, Dengyun [1 ]
Wang, Li-wei [1 ]
Lin, Jun [1 ]
En, Yunfei [1 ]
机构
[1] CEPREI Labs, Sci & Technol Reliabil Phys & Applicat Elect Comp, Guangzhou, Guangdong, Peoples R China
关键词
IP; quality; reliability; qualification;
D O I
10.1109/QRS-C.2017.104
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Field Programmable Gate Array (FPGA) system is widely used in deep learning application and cloud system for acceleration. Quality and reliability of IP block is essential to the successful development of today's complex hardware acceleration design. In this paper, we discuss the important issues of quality and reliability of digital soft IP, and propose a qualification measurement system that can evaluate IP quality. The metric system consists of eight categories to characterize IP quality. Based on this indicator system, we propose an IP qualification frameworks. As a case study, the proposed framework has been used to qualify three open source IP cores. The experimental results show that the proposed metric system and qualification framework can not only quantify the quality of IP, but also speed up the certification process and improve the accuracy of the certification results.
引用
收藏
页码:583 / 584
页数:2
相关论文
共 50 条
  • [41] Implementation of IP Core of Fast Sine and Cosine Operation through FPGA
    Shang, Yalei
    2012 INTERNATIONAL CONFERENCE ON FUTURE ENERGY, ENVIRONMENT, AND MATERIALS, PT B, 2012, 16 : 1253 - 1258
  • [42] Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA
    Yang, Pengfei
    Wang, Quan
    Zhang, Jiyang
    MULTIMEDIA TOOLS AND APPLICATIONS, 2016, 75 (08) : 4723 - 4733
  • [43] Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA
    Pengfei Yang
    Quan Wang
    Jiyang Zhang
    Multimedia Tools and Applications, 2016, 75 : 4723 - 4733
  • [44] Design of H.264 Video Decoding IP Core on FPGA
    Ru, Jiaxin
    Yang, Yingyun
    Yang, Yansi
    2014 FOURTH INTERNATIONAL CONFERENCE ON INSTRUMENTATION AND MEASUREMENT, COMPUTER, COMMUNICATION AND CONTROL (IMCCC), 2014, : 336 - 340
  • [45] Design and Realization of PMSM Vector Control IP Core Based on FPGA
    Hui, Qi
    Ya, Zhao
    ICEMS 2008: PROCEEDINGS OF THE 11TH INTERNATIONAL CONFERENCE ON ELECTRICAL MACHINES AND SYSTEMS, VOLS 1- 8, 2008, : 1325 - 1328
  • [46] Research on computing IP core for the digital signature algorithm
    Chu, JP
    Xu, YS
    Li, XJ
    Lai, ZS
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1329 - 1331
  • [47] 使用FPGA和IP Core实现定制缓冲管理
    Mark Wang
    今日电子, 2006, (11) : 91 - 94
  • [48] 32-bit Datapath AES IP Core Based on FPGA
    Tang, Hongwei
    INDUSTRIAL INSTRUMENTATION AND CONTROL SYSTEMS II, PTS 1-3, 2013, 336-338 : 1848 - 1851
  • [49] Designing a tiny and customizable TCP/IP core for low cost FPGA
    Charaabi, Lotfi
    Jaziri, Ibtihel
    2017 INTERNATIONAL CONFERENCE ON ENGINEERING & MIS (ICEMIS), 2017,
  • [50] Digital signature embedding technique for IP core protection
    Castillo, Encarnacion
    Garcia, Antonio
    Parrilla, Luis
    Morales, Diego P.
    Lloris, Antonio
    Meyer-Baese, Uwe
    2007 3RD SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2007, : 143 - +