6-T SRAM Cell Design with Gate-All-Around Silicon Nanowire MOSFETs

被引：0

作者：

Liao, Yi-Bo ^{[1
]}

Chiang, Meng-Hsueh ^{[2
]}

Damrongplasit, Nattapol ^{[3
]}

Liu, Tsu-Jae King ^{[3
]}

Hsu, Wei-Chou ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Inst Microelect, Tainan 701, Taiwan

[2] Natl Ilan Univ, Dept Elect Engn, Yilan 260, Taiwan

[3] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

引用

页数：2

共 50 条

[41] Modeling of nanoscale gate-all-around MOSFETs
Jiménez, D
Sáenz, JJ
Iñíguez, B
Suñé, J
Marsal, LF
Pallarès, J
[J]. IEEE ELECTRON DEVICE LETTERS, 2004, 25 (05) : 314 - 316
[42] CMOS-Compatible Gate-All-Around Silicon Nanowire detector
Ziaei-Moayyed, Maryam
Okandan, Murat
[J]. 2011 IEEE SENSORS, 2011, : 1608 - 1611
[43] Vertical silicon-nanowire formation and gate-all-around MOSFET
Yang, B.
Buddharaju, K. D.
Teo, S. H. G.
Singh, N.
Lo, G. Q.
Kwong, D. L.
[J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29 (07) : 791 - 794
[44] High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling
Bangsaruntip, S.
Cohen, G. M.
Majumdar, A.
Zhang, Y.
Engelmann, S. U.
Fuller, N. C. M.
Gignac, L. M.
Mittal, S.
Newbury, J. S.
Guillorn, M.
Barwicz, T.
Sekaric, L.
Frank, M. M.
Sleight, J. W.
[J]. 2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 272 - 275
[45] HIGH PERFORMANCE AND HIGHLY UNIFORM METAL HI-K GATE-ALL-AROUND SILICON NANOWIRE MOSFETS
Sleight, J.
Bangsaruntip, S.
Cohen, G.
Majumdar, A.
Zhang, Y.
Engelmann, S.
Fuller, N.
Gignac, L.
Mittal, S.
Newbury, J.
Barwicz, T.
Frank, M.
Guillorn, M.
[J]. ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2010, 28 (01): : 179 - 189
[46] Analog and RF analysis of gate all around silicon nanowire MOSFETs
Liu, Linjie
Han, Qinghua
Makovejev, Sergej
Trellenkamp, Stefan
Raskin, Jean-Pierre
Mantl, Siegfried
Zhao, Qing-Tai
[J]. 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017), 2017, : 176 - 179
[47] Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications
Yin, Yiheng
Zhang, Zhaofu
Zhong, Hongxia
Shao, Chen
Wan, Xuhao
Zhang, Can
Robertson, John
Guo, Yuzheng
[J]. ACS APPLIED MATERIALS & INTERFACES, 2021, 13 (02) : 3387 - 3396
[48] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
Dong, Xiaoqiao
Li, Ming
Zhang, Wanrong
Yang, Yuancheng
Chen, Gong
Sun, Shuang
Wang, Jianing
Xu, Xiaoyan
An, Xia
[J]. SCIENCE CHINA-INFORMATION SCIENCES, 2020, 63 (10)
[49] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
Xiaoqiao Dong
Ming Li
Wanrong Zhang
Yuancheng Yang
Gong Chen
Shuang Sun
Jianing Wang
Xiaoyan Xu
Xia An
[J]. Science China Information Sciences, 2020, 63
[50] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
Xiaoqiao DONG
Ming LI
Wanrong ZHANG
Yuancheng YANG
Gong CHEN
Shuang SUN
Jianing WANG
Xiaoyan XU
Xia AN
[J]. Science China(Information Sciences), 2020, 63 (10) : 288 - 290

← 1 2 3 4 5 →