6-T SRAM Cell Design with Gate-All-Around Silicon Nanowire MOSFETs

被引：0
|
作者：
Liao, Yi-Bo [1 ]
Chiang, Meng-Hsueh [2 ]
Damrongplasit, Nattapol [3 ]
Liu, Tsu-Jae King [3 ]
Hsu, Wei-Chou [1 ]
机构：
[1] Natl Cheng Kung Univ, Dept Elect Engn, Inst Microelect, Tainan 701, Taiwan
[2] Natl Ilan Univ, Dept Elect Engn, Yilan 260, Taiwan
[3] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA) | 2013年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.
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页数：2
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