Gate-all-around twin silicon nanowire SONOS memory

被引：26

作者：

Suk, Sung Dae ^{[1
]}

Yeo, Kyoung Hwan ^{[1
]}

Cho, Keun Hwi ^{[1
]}

Li, Ming ^{[1
]}

Yeoh, Yun young ^{[1
]}

Hong, Ki-Ha ^{[4
]}

Kim, Sung-Han ^{[3
]}

Koh, Young-Ho ^{[2
]}

Jung, Sunggon ^{[2
]}

Jang, WonJun ^{[2
]}

Kim, Dong-Won ^{[1
]}

Park, Donggun ^{[1
]}

Ryu, Byung-Il ^{[1
]}

机构：

[1] Samsung Elect Co, Device Res Team, San 24, Yongin 449711, Kyoungi Do, South Korea

[2] Samsung Elect Co, PD Team, Yongin 449711, Kyoungi Do, South Korea

[3] Samsung Elect Co, Team MTT2, Yongin 449711, Kyoungi Do, South Korea

[4] SAIT, Yongin 449711, Kyoungi Do, South Korea

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339760

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed gate-all-around (GAA) SONOS with ultra thin twin silicon nanowires for the first time. By using channel hot electron injection (CHEI) and hot hole injection (HHI) mechanisms, program speed of 1 mu s at V-d=2 V, V-g =6 V and erase speed of 1 ms at V-d=4.5 V, V-g=-6 V are achieved with 2 similar to 3 nm nanowire and 30 nm gate. Nanowire size below 10 nm dependencies on V, shift (AV,) and the program/erase (P/E) characteristics are investigated. As nanowire diameter (d(nw)) decreases, faster program speed and larger Delta V-th are observed.

引用

页码：142 / +

页数：2

共 50 条

[1] Si-nanowire based gate-all-around nonvolatile SONOS memory cell
Fu, J.
Singh, N.
Buddharaju, K. D.
Teo, S. H. G.
Shen, C.
Jiang, Y.
Zhu, C. X.
Yu, M. B.
Lo, G. Q.
Balasubramanian, N.
Kwong, D. L.
Gnani, E.
Baccarani, G.
[J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29 (05) : 518 - 521
[2] Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory
Seo, Joo Yun
Lee, Sang-Ho
Park, Se Hwan
Kim, Wandong
Kim, Do-Bin
Park, Byung-Gook
[J]. INTERNATIONAL JOURNAL OF NANOTECHNOLOGY, 2014, 11 (1-4) : 116 - 125
[3] Hot carrier and PBTI induced degradation in silicon nanowire gate-all-around SONOS MOSFETs
Choi, Jin Hyung
Han, Jin-Woo
Yu, Chong Gun
Park, Jong Tae
[J]. MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 2325 - 2328
[4] A Study on Gate-All-Around (GAA) Polycrystalline Silicon Channel SONOS Flash Memory
Seo, Joo Yun
Lee, Sang-Ho
Kim, Yoon
Park, Se Hwan
Kim, Wandong
Kim, Do-Bin
Park, Byung-Gook
[J]. PROCEEDINGS OF THE 2013 IEEE 5TH INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC), 2013, : 69 - 71
[5] Characteristics of Elliptical Gate-All-Around SONOS Nanowire With Effective Circular Radius
Lee, Myoung-Sun
Park, Byung-Gook
Cho, Il Hwan
Lee, Jong-Ho
[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (11) : 1613 - 1615
[6] Modeling of gate-all-around charge trapping SONOS memory cells
Gnani, E.
Reggiani, S.
Gnudi, A.
Baccarani, G.
Fu, J.
Singh, N.
Lo, G. Q.
Kwong, D. L.
[J]. SOLID-STATE ELECTRONICS, 2010, 54 (09) : 997 - 1002
[7] Reliability Improvement of Gate-All-Around Junctionless SONOS Memory by Joule Heat From Inherent Nanowire Current
Lee, Jung-Woo
Han, Joon-Kyu
Kim, Myung-Su
Yu, Ji-Man
Jung, Jin-Woo
Yun, Seong-Yun
Choi, Yang-Kyu
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (11) : 6133 - 6138
[8] Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture
Fu, J.
Jiang, Y.
Singh, N.
Zhu, C. X.
Lo, G. Q.
Kwong, D. L.
[J]. IEEE ELECTRON DEVICE LETTERS, 2009, 30 (03) : 246 - 249
[9] Gate-All-Around Silicon Nanowire Devices: Are these the Future of CMOS?
Lo, G. Q.
Singh, N.
Rustagi, S. C.
Buddharaju, K. D.
Balasubramanian, N.
Kwong, D. L.
[J]. SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES, 2008, 16 (10): : 729 - 729
[10] Fully gate-all-around silicon nanowire CMOS devices
Singh, N.
Buddharaju, K. D.
Agarwal, A.
Rustagi, S. C.
Lo, G. Q.
Balasubramanian, N.
Kwong, D. L.
[J]. SOLID STATE TECHNOLOGY, 2008, 51 (05) : 34 - 37

← 1 2 3 4 5 →