Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

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Xiaoqiao Dong
Ming Li
Wanrong Zhang
Yuancheng Yang
Gong Chen
Shuang Sun
Jianing Wang
Xiaoyan Xu
Xia An
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[1] Peking University,Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics
[2] Beijing University of Technology,Faculty of Information Technology
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