Implementation of Low Power Flash ADC By Reducing Comparators

被引：0
|
作者：
Megha, R. [1 ]
Pradeepkumar, K. A. [1 ]
机构：
[1] Amrita Vishwa Vidyapeetham, Amrita Sch Engn, Dept Elect & Commun Engn, Ettimadai, India
来源：
2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2014年
关键词：
low power; flash ADC; CMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The need for a high speed and low power ADC is very essential for various applications. Flash ADCs are always the architecture choice where maximum sample rate and moderate resolution is needed. Even though flash ADC is the fastest type available it takes enormous amount of IC real estate to implement. The main disadvantage of flash ADC is that it need large area and dissipate large amount of power. To overcome this complexity number of comparators are reducing by using multiplexers. Here the multiplexers are used to generate reference voltages. A 4-bit CMOS based flash ADC is presenting, which uses reduced comparator and multiplexer based architecture. Here both the analog and the digital parts of the proposed ADC are completely modified. This architecture uses only 4 comparators for a 4 bit ADC. This 4-bit ADC is designed and simulated in Hspice with 1.2 V supply voltage.
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页数：5
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