6-Bit low power low area frequency modulation based flash ADC

被引：0

作者：

Diduck, Q ^{[1
]}

Margala, M ^{[1
]}

机构：

[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 6-bit Frequency Modulation based ADC design. The demonstrated design yields a device that uses less than 10% of the power of comparable designs. In addition, this architecture provides a simple and logical way to trade sampling rate for accuracy. The presented device has a power consumption of 30 mW while operating at approximately 1.05 GSamples/Sec with an INL and DNL values of 0.23 and 0.4/-0.3 LSB respectively. The design has been implemented in an 1.8 Volt 0.18 mum CMOS process.

引用

页码：137 / 140

页数：4

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