Low power current-mode algorithmic ADC in half flash (BCD)

被引：0
|
作者：
Chuenarom, S. [1 ]
Maitreechit, S. [1 ]
Roengruen, P. [2 ]
Tipsuwarnpron, V. [2 ]
机构：
[1] SouthEast Asia Univ, Fac Engn, Dept Elect Engn, Bangkok 10160, Thailand
[2] King Mongkuts Inst Technol, Fac Engn, Bangkok 10520, Thailand
来源：
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年
关键词：
ADC; active current mirror; CMOS; power consumed;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a principle of analog to digital converter (ADC) based on current mode half flash (BCD). This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. It use a current injection technique to increase the speed of current mirrors, low power and algorithmic ADC application is presented. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.5 mu m which is capable to the slowest conversion time is less than 5.2nS, resulting in a conversion rate of more than 195 MHz, power consumed 1 mW, input current 0-60 mu A and single 2.5V supply.
引用
收藏
页码：175 / +
页数：2
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