Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

With the continuous advent of CMOS, process technologies is extending threat to the noise immune capability of CMOS circuits and the power consumed by them. In present day scenario, though there are a lot of techniques that exist for power reduction, the study of power-supply noise (PSN) based on those techniques is almost unattended in literature. Modern clock gating is one of the best techniques to reduce dynamic and static power dissipation by curbing down the switching activity of the operating clock as well as blocking the direct path between the power lines during logic transition. Therefore, in this paper, we have incorporated gating logic to offer solution to PSN occurrence in CMOS circuits by controlling di/dt, which is generated by the linear current ramp of present day high performance CPU. It is witnessed that, the gated architectures generate very less di/dt with respect to their non-gated counterpart, resulting a noted amount of reduction in PSN.