Evaluation of power supply noise in CMOS and low noise logic cells

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) radiation. In this paper, two new modified low-noise logic styles - Complementary-CBL, (C-CBL) and Enhanced-CSL (E-CSL) are presented in which the di/dt noise due to the switching is reduced greatly with respect to standard CMOS (SCMOS) circuits. Furthermore, a comparison with existing alternative low noise techniques shows that, for the same supply voltage and the same power consumption, the Enhanced-CSL circuits have smaller area, higher noise margins and smaller propagation delay.