Impact of dual-k spacer on analog performance of underlap FinFET

被引:32
|
作者
Nandi, Ashutosh [1 ]
Saxena, Ashok K. [1 ]
Dasgupta, S. [1 ]
机构
[1] Indian Inst Technol Roorkee, Dept Elect & Comp Engn, Roorkee 247667, Uttarakhand, India
关键词
Short channel effect (SCE); Dual-k spacer; Figures of merit (FOM); Electrostatic integrity (EI); Intrinsic gain; Cutoff frequency; GATE; DESIGN; TRANSISTORS; EXTENSION; CIRCUITS; DEVICE; RF;
D O I
10.1016/j.mejo.2012.06.001
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and total gate capacitance. In this paper we have used dual-k spacers in underlap FinFETs to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out the gate sidewall fringing fields, thereby, increasing transconductance and reducing output conductance with increase in total gate capacitance. At 16 nm gate lengths, we have observed that, the intrinsic gain of dual-k spacer based FinFET can be increased by more than 100% (>6 dB) without affecting cutoff frequency and maximum oscillation frequency, as compared to conventional single spacer based FinFET. Improvement in cutoff frequency by 11% and maximum oscillation frequency by 5% can be achieved, when the gate lengths are scaled down to 12 nm, in addition to 2.75 times (8.8 dB) increase in intrinsic gain. (C) 2012 Elsevier Ltd. All rights reserved.
引用
收藏
页码:883 / 887
页数:5
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