Improving the performance of dual-k spacer underlap Double Gate TFET

被引：6

作者：

Chauhan, Abhinav ^{[1
]}

Saini, Gaurav ^{[1
,2
]}

Yerur, Pavan Kumar ^{[3
]}

机构：

[1] Natl Inst Technol, School VLSI Design & Embedded Syst, Kurukshetra, Haryana, India

[2] Natl Inst Technol, Dept ECE, Kurukshetra, Haryana, India

[3] Microsemi Storage Solut Pvt Ltd, Bangalore, Karnataka, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2018年 / 124卷

关键词：

Band-to-band tunneling (BTBT); Double Gate (DG) tunnel FET; Dual-k spacer; On-current; Subthreshold swing (SS); TUNNEL; IMPROVEMENT;

D O I：

10.1016/j.spmi.2018.10.006

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

In this paper, the effect of dual-k spacer is investigated on underlap Double-Gate TFET (DGTFET) for low-k and high-k gate dielectrics. Simulation study shows that the position of dual-k spacer junction must be aligned with metallurgical junction (tunneling junction) between source and channel region for improved performance. DGTFET structure is optimized to improve the performance metrics such as on-current (I-on), off-current (I-off) and subthreshold swing (SS) for low-k and high-k gate dielectrics. An optimized DGTFET shows impressive improvements in I-on and average SS when compared to their conventional DGTFET structures. Optimized DGTFET with SiO2 and HfO2 as gate dielectric shows improvements in I-on by 15874.03% and 525.71%, average SS by 46.17% and 25.15% respectively when compared to their conventional counterpart. Proposed optimization is useful in enhancing the performance of dual-k spacers based DGTFETs.

引用

页码：79 / 91

页数：13

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