共 50 条
- [1] An Efficient VLSI Architecture for Full-Search Block Matching Algorithms [J]. Journal of VLSI signal processing systems for signal, image and video technology, 1997, 15 : 275 - 282
- [2] An efficient VLSI architecture for full-search block matching algorithms [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 15 (03): : 275 - 282
- [3] PARAMETERIZABLE VLSI ARCHITECTURES FOR THE FULL-SEARCH BLOCK-MATCHING ALGORITHM [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (10): : 1309 - 1316
- [5] Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm [J]. Journal of VLSI signal processing systems for signal, image and video technology, 1997, 17 : 225 - 240
- [6] Cost effective VLSI architectures for full-search block-matching motion estimation algorithm [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 17 (2-3): : 225 - 240
- [7] Design and implementation of efficient VLSI architectures for full-search block-matching motion estimation [J]. PROCEEDINGS OF THE THIRD INTERNATIONAL SYMPOSIUM ON INSTRUMENTATION SCIENCE AND TECHNOLOGY, VOL 1, 2004, : 616 - 620
- [8] Buffer size optimization for full-search block matching algorithms [J]. IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS, 1997, : 76 - 85
- [9] Systolic array architectures for full-search block matching motion estimation [J]. THIRD INTERNATIONAL WORKSHOP ON DIGITAL AND COMPUTATIONAL VIDEO, PROCEEDINGS, 2002, : 108 - 115