Systolic array architectures for full-search block matching motion estimation

被引：2
|
作者：
Elgamel, MA [1 ]
Nallamilli, BR [1 ]
Bayoumi, MA [1 ]
Mashaly, S [1 ]
机构：
[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA
来源：
THIRD INTERNATIONAL WORKSHOP ON DIGITAL AND COMPUTATIONAL VIDEO, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/DCV.2002.1218750
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents various systolic architectures for full search block matching motion estimation. Along with one dimensional (N PE's) and Two Dimensional (N-2 PE's) systolic array architectures using 2N, 3N,.......,N-2-N Processing Elements are also presented Each of the architectures is analyzed and then compared with others in terms of Power Consumption, Area, Delay and Noise. Simulation and Analysis results of the architectures are presented. The results show the trade-off between the number of Processing elements used, Processing rate and Power dissipation.
引用
收藏
页码：108 / 115
页数：8
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