A NOVEL MODULAR SYSTOLIC ARRAY ARCHITECTURE FOR FULL-SEARCH BLOCK MATCHING MOTION ESTIMATION

被引：83
|
作者：
YEO, HG
HU, YH
机构：
[1] Department of Electrical and Computer Engineering, University of Wisconsin, Madison
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1995年 / 5卷 / 05期
关键词：
D O I：
10.1109/76.473553
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a novel modular systolic array architecture for the full search block matching motion estimation algorithm (FBMA) is presented. The design efforts are focused on matching the array computation to system level input/output constraints. Compared to previously proposed FBMA architectures, this new architecture delivers highest throughput rate, achieves 100% processor utilization, requires much fewer input/output lines (pin count), and is linearly scalable. As such, this architecture offers a feasible solution for progressive-scan HDTV picture format.
引用
收藏
页码：407 / 416
页数：10
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