Buffer size optimization for full-search block matching algorithms

被引：1
|
作者：
Yeh, YH
Lee, CY
机构：
来源：
IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/ASAP.1997.606814
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint As a result a systematic design procedure for buffer optimization is derived to reduce realization cost.
引用
收藏
页码：76 / 85
页数：10
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