Design And Implementation Of Area- Delay-Power Efficient CSLA Based 32-Bit Array Multiplier

被引：0

作者：

Afreen, N. Fahmina ^{[1
]}

Basha, M. Mahaboob ^{[2
]}

Das, S. Mohan ^{[2
]}

机构：

[1] SVREC, Nandyal, AP, India

[2] SVREC, Dept ECE, Nandyal, AP, India

来源：

2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT) | 2017年

关键词：

CSLA; optimized CSLA; Area efficient; Array Multiplier; Low Power; CARRY-SELECT ADDER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Addition and Multiplication are two important mathematical operations that can be performed in every digital circuit. The performance of multiplier depends on adder, hence there is a need to use an efficient adder for multiplication. Definitely an efficient Adder can be utilized to enhance the performance of DSP system. This paper presents lower area, energy efficient 32-bit Array Multiplier based on optimized Carry Select Adder. The proposed Multiplier gives high performance by saving 41% power, less delay by 27% with less area by reducing the slices up to 11.83% and LUTs by 7.6% when compared to conventional CSLA based Array Multiplier.

引用

页码：1578 / 1582

页数：5

共 44 条

[1] Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
Vijayalakshmi, V.
Seshadri, R.
Ramakrishnan, S.
[J]. 2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN VLSI, EMBEDDED SYSTEM, NANO ELECTRONICS AND TELECOMMUNICATION SYSTEM (ICEVENT 2013), 2013,
[2] Design and Comparison of Power, Area and Delay of 32-bit Reversible MAC unit
Pandimeena, R.
Annapoorani, A.
Kaviya, T. D.
Rajalakshimi, A.
Dhanagopal, R.
[J]. 2020 6TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATION SYSTEMS (ICACCS), 2020, : 1412 - 1416
[3] Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures
Sharma, Richa
Kaur, Manjit
Singh, Gurmohan
[J]. 2015 INTERNATIONAL CONFERENCE ON INDUSTRIAL INSTRUMENTATION AND CONTROL (ICIC), 2015, : 960 - 964
[4] Implementation of 32-bit Area-Efficient Hybrid Modulo 2n+1 Adder and Multiplier
Asha, G. H.
Uday, J.
[J]. 2014 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2014, : 651 - 658
[5] VLSI Architecture for delay efficient 32-bit Multiplier using Vedic Mathematic sutras
Ram, G. Challa
Rani, D. Sudha
Balasaikesava, R.
Sindhuri, K. Bala
[J]. 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 1873 - 1877
[6] Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
Saha, P.
Banerjee, A.
Dandapat, A.
Bhattacharyya, P.
[J]. INTERNATIONAL JOURNAL ON SMART SENSING AND INTELLIGENT SYSTEMS, 2011, 4 (02): : 268 - 284
[7] High Speed, Area and Power Efficient 32-bit Vedic Multipliers
Mulkalapally, Mounika
Manning, Jacob
Gatewood, Paul
Nikoubin, Tooraj
[J]. 7TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT 2016), 2016,
[8] An Area-Efficient 32-bit Floating Point Multiplier using Hybrid GPPs Addition
Nesam, J. Jean Jenifer
Sivanantham, S.
[J]. 2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS), 2017,
[9] Design and Implementation of 32-bit MIPS-Based RISC Processor
Patra, Sumit
Kumar, Sunil
Verma, Swati
Kumar, Arvind
[J]. ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 747 - 757
[10] An efficient design of FSM based 32-bit unsigned high-speed pipelined multiplier using Verilog HDL
Abdullah-Al-Kafi
Rahman, Atul
Mahjabeen, Bushra
Rahman, Mahmudur
[J]. 2014 INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2014, : 164 - 167

← 1 2 3 4 5 →