An Area-Efficient 32-bit Floating Point Multiplier using Hybrid GPPs Addition

被引：0

作者：

Nesam, J. Jean Jenifer ^{[1
]}

Sivanantham, S. ^{[1
]}

机构：

[1] VIT Univ, Sch Elect Engn, Vellore, Tamil Nadu, India

来源：

2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS) | 2017年

关键词：

Floating point multiplier; Hybrid adder; Area-efficient multiplier; ARCHITECTURES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we proposed a new design of hybrid adder for area-efficient 32-bit floating point multiplier. By combining conventional ripple carry adder (RCA) and Wallace tree adder for adding Generated Partial Products (GPPs), the speed can be improved. Toom-3 multiplication method applied on 24x24 mantissa multiplier with a reduced complexity of (n(1.465)). Pre-determined Partial Products Generation (3PG) methods reduce the height of the GPPs to (N/3)/4 for N=24-bit unsigned operands. This is a contrast to Modified Booth Encoding (MBE) GPPs reduction height of N/2. This reduction can use to save area. The design is synthesized on TSMC 0.13 mu m CMOS with 62% less area when compared to MBE based FP multiplier.

引用

页数：4

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