Design And Implementation Of Area- Delay-Power Efficient CSLA Based 32-Bit Array Multiplier

被引：0

作者：

Afreen, N. Fahmina ^{[1
]}

Basha, M. Mahaboob ^{[2
]}

Das, S. Mohan ^{[2
]}

机构：

[1] SVREC, Nandyal, AP, India

[2] SVREC, Dept ECE, Nandyal, AP, India

来源：

2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT) | 2017年

关键词：

CSLA; optimized CSLA; Area efficient; Array Multiplier; Low Power; CARRY-SELECT ADDER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Addition and Multiplication are two important mathematical operations that can be performed in every digital circuit. The performance of multiplier depends on adder, hence there is a need to use an efficient adder for multiplication. Definitely an efficient Adder can be utilized to enhance the performance of DSP system. This paper presents lower area, energy efficient 32-bit Array Multiplier based on optimized Carry Select Adder. The proposed Multiplier gives high performance by saving 41% power, less delay by 27% with less area by reducing the slices up to 11.83% and LUTs by 7.6% when compared to conventional CSLA based Array Multiplier.

引用

页码：1578 / 1582

页数：5

共 44 条

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