Fault simulation and test algorithm generation for random access memories

被引：28

作者：

Wu, CF ^{[1
]}

Huang, CT ^{[1
]}

Cheng, KL ^{[1
]}

Wu, CW ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2002年 / 21卷 / 04期

关键词：

fault simulation; integrated-circuit testing; memory testing; RAM; semiconductor memory; test pattern generation;

D O I：

10.1109/43.992771

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.

引用

页码：480 / 490

页数：11

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