Modeling of nanoscale gate-all-around MOSFETs

被引：131
|
作者：
Jiménez, D
Sáenz, JJ
Iñíguez, B
Suñé, J
Marsal, LF
Pallarès, J
机构：
[1] Univ Autonoma Barcelona, Escola Tecn Super Engn, Dept Elect Engn, Barcelona, Spain
[2] Univ Autonoma Barcelona, Dept Fis Mat Condensada, Fac Ciencias, Barcelona, Spain
[3] Univ Rovira & Virgili, Escola Tecn Super Engn, Dept Engn Elect, Barcelona, Spain
来源：
IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 05期
关键词：
modeling; MOSFETs; quantum wires;
D O I：
10.1109/LED.2004.826526
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit. The current through the device is obtained by means of the Lan-dauer approach, being the barrier height the key parameter in the model. The exact solution of the Poisson's equation is obtained in order to deal with all the operation regions tracing properly the transitions between them.
引用
收藏
页码：314 / 316
页数：3
相关论文
共 50 条
  • [31] Low temperature single electron characteristics in gate-all-around MOSFETs
    Pott, Vincent
    Bouvet, Didier
    Boucart, Julien
    Tschuor, Lucas
    Moselund, Kirsten E.
    Ionescu, Adrian M.
    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 427 - +
  • [32] Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs
    Zou, Jibin
    Xu, Qiumin
    Luo, Jieying
    Wang, Runsheng
    Huang, Ru
    Wang, Yangyuan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (10) : 3379 - 3387
  • [33] Sensitivity of Gate-All-Around Nanowire MOSFETs to Process Variations-A Comparison With Multigate MOSFETs
    Wu, Yu-Sheng
    Su, Pin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (11) : 3042 - 3047
  • [34] Nanowire gate-all-around MOSFETs modeling: ballistic transport incorporating the source-to-drain tunneling
    Cheng, He
    Liu, Tiefeng
    Zhang, Chao
    Liu, Zhifeng
    Yang, Zhijia
    Nakazato, Kazuo
    Zhang, Zhipeng
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2020, 59 (07)
  • [35] A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs
    Butola, Rajat
    Li, Yiming
    Kola, Sekhar Reddy
    IEEE ACCESS, 2022, 10 : 71356 - 71369
  • [36] Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale
    Dey, S.
    Dash, T. P.
    Das, S.
    Mohapatra, E.
    Jena, J.
    Maiti, C. K.
    PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES KOLKATA CONFERENCE (IEEE EDKCON), 2018, : 137 - 141
  • [37] Local volume inversion and corner effects in triangular gate-all-around MOSFETs
    Moselund, Kirsten E.
    Bouvet, Didier
    Tschuor, Lucas
    Pott, Vincent
    Dainesi, Paolo
    Ionescu, Adrian M.
    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 359 - +
  • [38] InAs Nanowire Gate-All-Around MOSFETs by Heterogeneous Planar VLS Growth
    Zhang, Chen
    Choi, Wonsik
    Mohseni, Parsian
    Li, Xiuling
    2015 73RD ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2015, : 181 - 182
  • [39] InAs Gate-all-around Nanowire MOSFETs by Top-down Approach
    Wu, H.
    Lou, X. B.
    Si, M.
    Zhang, J. Y.
    Gordon, R. G.
    Tokranov, V.
    Oktyabrsky, S.
    Ye, P. D.
    2014 72ND ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2014, : 213 - +
  • [40] GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
    Junk, Yannik
    Frauenrath, Marvin
    Han, Yi
    Diaz, Omar Concepcion
    Bae, Jin-Hee
    Hartmann, Jean-Michel
    Gruetzmacher, Detlev
    Buca, Dan
    Zhao, Qing-Tai
    ESSDERC 2022 - IEEE 52ND EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2022, : 364 - 367
12345