Efficient SAT-based bounded model checking for software verification

被引:47
|
作者
Ivancic, Franio [1 ]
Yang, Zijiang [2 ]
Ganai, Malay K. [1 ]
Gupta, Aarti [1 ]
Ashar, Pranav [1 ]
机构
[1] NEC Labs Amer, Princeton, NJ 08540 USA
[2] Western Michigan Univ, Dept Comp Sci, Kalamazoo, MI 49008 USA
关键词
software verification; bounded model checking; SAT-based model checking;
D O I
10.1016/j.tcs.2008.03.013
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper discusses our methodology for formal analysis and automatic verification of software programs. It is applicable to a large subset of the C programming language that includes pointer arithmetic and bounded recursion. We consider reachability properties, in particular whether certain assertions or basic blocks are reachable in the source code, or whether certain standard property violations can occur. We perform this analysis via a translation to a Boolean circuit representation based on modeling basic blocks. The program is then analyzed by a back-end SAT-based bounded model checker, where each unrolling is mapped to one step in a block-wise execution of the program. The main Contributions of this paper are as follows: (1) Use of basic block-based unrollings With SAT-based bounded model checking of software programs. This allows us to take advantage of SAT-based learning inherent to the best performing bounded model checkers. (2) Various heuristics customized for models automatically generated from software, allowing a more efficient SAT-based analysis. (3) A prototype tool called F-SOFT has been implemented using Our methodology. We present experimental results based on multiple case studies including a C-based implementation of a network protocol, and compare the performance gains using the proposed heuristics. (c) 2008 Elsevier B.V. All rights reserved.
引用
下载
收藏
页码:256 / 274
页数:19
相关论文
共 50 条
  • [21] SAT-Based Model Checking without Unrolling
    Bradley, Aaron R.
    VERIFICATION, MODEL CHECKING, AND ABSTRACT INTERPRETATION, 2011, 6538 : 70 - 87
  • [22] Symmetry reduction in SAT-based model checking
    Tang, DJ
    Malik, S
    Gupta, A
    Ip, CN
    COMPUTER AIDED VERIFICATION, PROCEEDINGS, 2005, 3576 : 125 - 138
  • [23] Certifying proofs for SAT-based model checking
    Alberto Griggio
    Marco Roveri
    Stefano Tonetta
    Formal Methods in System Design, 2021, 57 : 178 - 210
  • [24] SAT-based unbounded symbolic model checking
    Kang, HJ
    Park, IC
    40TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2003, 2003, : 840 - 843
  • [25] SAT-based unbounded symbolic model checking
    Kang, HJ
    Park, IC
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (02) : 129 - 140
  • [26] Certifying proofs for SAT-based model checking
    Griggio, Alberto
    Roveri, Marco
    Tonetta, Stefano
    FORMAL METHODS IN SYSTEM DESIGN, 2021, 57 (02) : 178 - 210
  • [27] SAT-Based Fault Equivalence Checking in Functional Safety Verification
    Ai Quoc Dao
    Lin, Mark Po-Hung
    Mishchenko, Alan
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (12) : 3198 - 3205
  • [28] TACO: Efficient SAT-Based Bounded Verification Using Symmetry Breaking and Tight Bounds
    Galeotti, Juan P.
    Rosner, Nicolas
    Lopez Pombo, Carlos G.
    Frias, Marcelo F.
    IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 2013, 39 (09) : 1283 - 1306
  • [29] Improving SAT-based Bounded Model Checking by means of BDD-based approximate traversals
    Cabodi, G
    Nocco, S
    Quer, S
    JOURNAL OF UNIVERSAL COMPUTER SCIENCE, 2004, 10 (12) : 1693 - 1730
  • [30] Improving SAT-based bounded model checking by means of BDD-based approximate traversals
    Cabodi, G
    Nocco, S
    Quer, S
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 898 - 903