Statistical Analysis of Off-chip Power-Integrity for Multicore Systems

This work suggests a statistical off-chip PI analysis approach for multicore systems to enable effective elimination of inherent pessimism of the conventional worst-case PI analysis. The proposed approach aims to investigate the probability distribution of voltage drops by generating and using random-delay scenarios of multiple cores as follows. First, the proposed approach generates a random-delay scenario of multiple cores by using a given one-core current scenario, under the assumption that the multiple cores in a system work in the same operation but not in a synchronous mode. In order to get a random-delay scenario, the proposed approach generates and applies random delays to the given current scenario for all cores. Next, the delayed current scenarios for all cores are combined at the bump. The accumulated current scenario represents asynchronous operations of multiple cores. After generating the scenario, a voltage drop at a bump is calculated by applying the generated random-delay scenario. This procedure is repeated until the amount of data are sufficiently collected to generate the reliable probability distribution of voltage drops. In the experimental study with 5,000 random-delay scenarios, we found that 3-sigma level of voltage drops is 8.6 % smaller than the required voltage drop specification, while the voltage drop of the worst-case scenario is 23.2 % larger than the voltage drop specification. Therefore, the results indicate that it is necessary to adjust the design cost more efficiently according to the statistical PI analysis.