CMOS Implementation of a Novel High Speed 4:2 Compressor for Fast Arithmetic Circuits

This paper deals with the design and analysis of a new 4-2 compressor which can be used in high-speed multipliers. The proposed compressor features eliminated glitch at the output waveform. By optimum tuning of the width of the transistors, C (out) is produced more quickly, and therefore higher operating speeds can be achieved. The effect of process variation on the circuit has been studied and a new structure is proposed to overcome the effect of process variation by utilizing a reference voltage generator circuit. A 32 x 32-bit multiplier has been developed utilizing these compressors in order to evaluate the new compressor in a practical environment. The total multiplier circuit was simulated with HSPICE simulator (BSIM3v3 parameters) using CMOS standard cell library of 0.18 mu m and the Layouts were extracted with Cadence Virtuoso v 5.1 Layout Plus tool. The simulation results represent 185 x 10(-3) pj Power-Delay-Product (PDP) and 40 pj x ps Energy Delay Product (EDP) with 221 ps delay from input to output.