Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

被引:0
|
作者
Razi, Keyvan Farhang [1 ]
Schmid, Alexandre [1 ]
机构
[1] Swiss Fed Inst Technol Lausanne EPFL, Inst Elect & Micro Engn, Lausanne, Switzerland
基金
瑞士国家科学基金会;
关键词
RISC processor; Epileptic seizure detection; Programmable medical implant; Feature ranking;
D O I
10.1109/LASCAS56464.2023.10108303
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-power 32-bit MIPS-based RISC processor which consists of five stages and supports three types of instructions. This work exhibits superiority over the existing seizure detectors since the RISC processor can be programmed by physicians to define different therapy options that are safe and efficient for each patient. Moreover, the patients have the opportunity of adjusting the seizure detection parameters by switching between different therapy options available under the permission of their physicians in order to enhance seizure detection performance. Seizure detection is performed by exploiting widely-used computational complexity-efficient time-domain features in conjunction with a feature ranking unit. The classification task is conducted by three logical functions which are defined to reach specific therapeutic goals such as rapid seizure detection and minimum false positive detections. Patients can dynamically adjust the critical seizure detection parameters such as sensitivity, specificity, and detection delay to make the medical device compatible with their current condition. The proposed programmable seizure detector is implemented on an ALTERA DE10-standard board with a Cyclone V FPGA and tested on 10 patients with 65 seizure events of the SWEC-ETHZ database from the Inselspital Bern which reveals a low dynamic power consumption of 0.78 mW which confirms its compatibility with low-power implantable devices.
引用
收藏
页码:149 / 152
页数:4
相关论文
共 50 条
  • [31] 32-bit RISC CPU Based on MIPS
    Yi, Kui
    Ding, Yue-Hua
    [J]. PROCEEDINGS OF THE 2009 SECOND PACIFIC-ASIA CONFERENCE ON WEB MINING AND WEB-BASED APPLICATION, 2009, : 124 - 128
  • [32] A 32-BIT RISC CPU IMPLEMENTED IN GAAS
    GEIDEMAN, WA
    NIEDERLAND, RA
    HARRINGTON, DL
    [J]. MICROPROCESSING AND MICROPROGRAMMING, 1990, 30 (1-5): : 127 - 133
  • [33] Design of a 32-bit embedded RISC microprocessor
    [J]. 2000, Sci Press (37):
  • [34] Design and Implementation of Low Power Reservation Station of a 32-bit DLX-RISC processor
    Albuquerque, Nathaniel
    Prakash, Kritika
    Mehra, Anu
    Gaur, Nidhi
    [J]. PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE (ICIS), 2016, : 217 - 221
  • [35] Linearized power detector with 32-bit RISC microprocessor for 2.45 GHz ISM band
    Brezovic, Zdenko
    [J]. PROCEEDINGS OF THE 14TH CONFERENCE ON MICROWAVE TECHNIQUES: COMITE 2008, 2008, : 25 - 27
  • [36] A 32-BIT PROCESSOR ON A 16-BIT BUS
    BUDZINSKI, M
    [J]. CONTROL ENGINEERING, 1986, 33 (03) : 84 - 84
  • [37] A 500-MHZ, 32-BIT, 0.4-MU-M CMOS RISC PROCESSOR
    SUZUKI, K
    YAMASHINA, M
    NAKAYAMA, T
    IZUMIKAWA, M
    NOMURA, M
    IGURA, H
    HEIUCHI, H
    GOTO, J
    INOUE, T
    KOSEKI, Y
    ABIKO, H
    OKABE, K
    ONO, A
    YANO, Y
    YAMADA, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) : 1464 - 1473
  • [38] IMPLEMENTATION OF 32-BIT RISC PROCESSOR INCORPORATING HARDWARE CONCURRENT ERROR-DETECTION AND CORRECTION
    ELLIOTT, ID
    SAYERS, IL
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1990, 137 (01): : 88 - 102
  • [39] Design and Performance Analysis of One 32-bit Dual Issue RISC Processor for Embedded Application
    Huang, Xiaoping
    Fan, Xiaoya
    Zhang, Shengbing
    [J]. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1819 - 1822
  • [40] Hitachi's 32-bit RISC hits #1
    Weiss, R
    [J]. COMPUTER DESIGN, 1996, 35 (04): : 28 - +