An Enhanced StrongArm Dynamic Latch Comparator for Low-Power and High-Speed Applications

In this work, an enhanced StrongArm latch comparator for high speed application is proposed. It uses a customized charge steering as dynamic biasing. The tail current of the proposed circuit is built to drop quickly, decreasing the average current flowing through the input transistor. In addition, two clock switches are added at nodes P and Q to raise the input device in weak inversion during amplification and also to improve the tail current's discharging rate. The MOSCAP is utilized as a load throughout the entire circuit to enhance the input referred offset. The proposed comparator is simulated utilizing 65nm CMOS technology. A high comparison speed of 2GHz is achieved. Deep analysis and simulations show that the proposed design achieved improved power consumption of 9.7 mu W, a time delay of 87.9ps at Delta Vin=0.7 mV, input referred offset of 3.8mV and energy-delay product 0.43fJ/GHz. The figure of merit of the designed comparator is 0.38nJ & sdot;mu V2 & sdot;ns, which is improved by 36.7%.