A low-power and high-speed D flip-flop using a single latch

被引：1

作者：

Chang, RC ^{[1
]}

Hsu, LC ^{[1
]}

Sun, MC ^{[1
]}

机构：

[1] Natl Chunghsing Univ, Dept Elect Engn, Taichung 40227, Taiwan

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2002年 / 11卷 / 01期

关键词：

D O I：

10.1142/S0218126602000239

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse, Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

引用

页码：51 / 55

页数：5

共 50 条

[1] A high-speed low-power D flip-flop
Chandrasekaran, R
Lian, Y
Rana, RS
[J]. 2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 152 - 155
[2] TESTS CONFIRM HIGH-SPEED LOW-POWER FLIP-FLOP
不详
[J]. ELECTRONICS WORLD & WIRELESS WORLD, 1991, 97 (1667): : 724 - 724
[3] A novel low-power and high-speed master-slave D flip-flop
Gao, Hongli
Qiao, Fei
Wei, Dingli
Yang, Huazhong
[J]. TENCON 2006 - 2006 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2006, : 409 - +
[4] Design and Analysis of High-Performance and Low-Power Quaternary Latch, Quaternary D Flip-Flop and XY Flip-Flop
Shadwani, Mayank
Bansal, Urvashi
[J]. INDIAN JOURNAL OF PURE & APPLIED PHYSICS, 2022, 60 (12) : 1004 - 1015
[5] The Cross Charge-control Flip-Flop: a low-power and high-speed flip-flop suitable for mobile application SoCs
Hirata, A
Nakanishi, K
Nozoe, M
Miyoshi, A
[J]. 2005 Symposium on VLSI Circuits, Digest of Technical Papers, 2005, : 306 - 307
[6] Low-power and High-speed SerDes with New Dynamic Latch and Flip-flop for Optical Interconnect in 180 nm CMOS Technology
Sangirov, Jamshid
Ukaegbu, Ikechi Augustine
Lee, Tae-Woo
Cho, Mu Hee
Park, Hyo-Hoon
[J]. OPTOELECTRONIC INTERCONNECTS AND COMPONENT INTEGRATION XI, 2011, 7944
[7] NOVEL HIGH-SPEED FLIP-FLOP CIRCUIT WITH LOW-POWER CONSUMPTION USING GAAS JUNCTION FETS
TAKANO, C
WADA, M
KASAHARA, J
[J]. ELECTRONICS LETTERS, 1991, 27 (09) : 764 - 765
[8] A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links
Choi, Junung
Cho, Jaeik
Choi, Won Joon
Lee, Myungguk
Kim, Byungsub
[J]. 2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2022, : 19 - 20
[9] A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications
Wang, JS
Yang, PH
[J]. ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : A93 - A96
[10] A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS
You, Heng
Yuan, Jia
Tang, Weidi
Yu, Zenghui
Qiao, Shushan
[J]. ELECTRONICS, 2020, 9 (05):

← 1 2 3 4 5 →