Design of Low Power and High Speed Dynamic Latch Comparator using 180 nm Technology

被引：0

作者：

Lahariya, Aparna ^{[1
]}

Gupta, Anshu ^{[1
]}

机构：

[1] Mody Univ Sci & Technol, Elect & Commun Engn, Laxmangarh, Rajasthan, India

来源：

2015 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMPUTING AND CONTROL (ISPCC) | 2015年

关键词：

Preamplifier Based Comparator; Self Biasing Comparator; dynamic latch comparator;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, Low power and high speed regenerative double tail dynamic latch comparator for a application of high speed analog to digital converter has been designed. A proposed comparator has increased the speed of the circuit. The proposed regenerative double tail dynamic latch comparator has a good performance to conventional comparator. It is designed in Cadence UMC 180 nm CMOS process with a supply voltage of 1.8 V. The slew rate is increased, whereas rise time, fall time and settling time are decreased.. The improved values positive slew rate and negative slew rate are 7.61 kV/mu s and 13.25 kV/mu s. The delay and power consumption is 5 mu s and 4.24 nW respectively.

引用

页码：129 / 134

页数：6

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