On test set generation for efficient path delay fault diagnosis

被引:0
|
作者
Tekumalla, Ramesh C. [1 ]
机构
[1] Intel Corp, Hillsboro, United States
关键词
D O I
暂无
中图分类号
学科分类号
摘要
Integrated circuit testing
引用
收藏
页码:343 / 348
相关论文
共 50 条
  • [31] Low Power Test Generation for Path Delay Faults
    Kumar, M. M. Vaseekar
    Tragoudas, S.
    [J]. JOURNAL OF LOW POWER ELECTRONICS, 2005, 1 (02) : 194 - 205
  • [32] On Accelerating Path Delay Fault Simulation of Long Test Sequences
    Huang, I-De
    Chang, Yi-Shing
    Natarajan, Suriyaprakash
    Sharma, Ramesh
    Gupta, Sandeep K.
    [J]. 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 710 - +
  • [33] A delay fault model for at-speed fault simulation and test generation
    Pomeranz, Irith
    Reddy, Sudhakar M.
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, : 257 - +
  • [34] Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults
    Chary, S
    Bushnell, ML
    [J]. 19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 413 - 418
  • [35] Fault Simulation and Test Generation for Clock Delay Faults
    Higami, Yoshinobu
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Saluja, Kewal K.
    [J]. 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [36] Path delay fault diagnosis and coverage - A metric and an estimation technique
    Sivaraman, M
    Strojwas, AJ
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (03) : 440 - 457
  • [37] Delay fault diagnosis in sequential circuits based on path tracing
    Girard, P
    Landrault, C
    Pravossoudovitch, S
    Rodriguez, B
    [J]. INTEGRATION-THE VLSI JOURNAL, 1995, 19 (03) : 199 - 218
  • [38] DELAY FAULT-DIAGNOSIS BY CRITICAL-PATH TRACING
    GIRARD, P
    LANDRAULT, C
    PRAVOSSOUDOVITCH, S
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 1992, 9 (04): : 27 - 32
  • [39] Efficient delay test generation for modular circuits
    Ravikumar, CP
    Agrawal, N
    Agarwal, P
    [J]. SIXTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1996, : 220 - 225
  • [40] Reducibility of sequential test generation to combinational test generation for several delay fault models
    Iwagaki, T
    Ohtake, S
    Fujiwara, H
    [J]. ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 58 - 63