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- [21] BIST scheme for low heat dissipation and reduced test application time IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 239 - +
- [22] Symmetry Measure for Memory Test and Its Application in BIST Optimization JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (06): : 753 - 766
- [23] Exploiting test resource optimization in data path synthesis for BIST NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 342 - 343
- [25] Optimization and implement technique for test generation in the design of BIST architecture ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 1650 - 1654
- [26] BIST scheme based on two-dimensional test data compression Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2009, 21 (04): : 481 - 486
- [27] A Comprehensive TCAM Test Scheme: An Optimized Test Algorithm Considering Physical Layout and Combining Scan Test with At-Speed BIST Design ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 186 - +
- [28] Instruction based BIST for board/system level test of external memories and internconnects INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 961 - 970
- [29] Test of the ATLAS pion calibration scheme in the ATLAS combined test beam XIII INTERNATIONAL CONFERENCE ON CALORIMETRY IN HIGH ENERGY PHYSICS, 2009, 160
- [30] A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS RESEARCH AND MECHATRONICS ENGINEERING, 2015, 121 : 354 - 357