共 50 条
- [32] Implementing a scheme for external deterministic self-test 23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 101 - 106
- [33] Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement 2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
- [34] Reduction of Test Power and Data volume in BIST Scheme Based on Scan Slice Overlapping ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2737 - +
- [35] Test cost minimization for hybrid BIST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 283 - 291
- [36] Salvaging test windows in BIST diagnostics 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 416 - 425
- [37] Test Power Aware STUMP BIST 2015 INTERNATIONAL CONFERENCE ON SMART TECHNOLOGIES AND MANAGEMENT FOR COMPUTING, COMMUNICATION, CONTROLS, ENERGY AND MATERIALS (ICSTM), 2015, : 434 - 438
- [39] On using deterministic test sets in BIST 6TH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS, 2000, : 127 - 132
- [40] Clustering compression of test pattern for BIST Li, L. (lijian.li@ia.ac.cn), 1600, Institute of Computing Technology (26):