Resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays

被引:0
|
作者
Kim, Jung H. [1 ]
Rhee, Phill K. [1 ]
机构
[1] Univ of Southwest Louisiana, Lafayette, United States
关键词
VLSI circuits;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:317 / 330
相关论文
共 50 条
  • [31] An improved reconfiguration method for degradable processor arrays using genetic algorithm
    Fukushima, Yusuke
    Fukushi, Masaru
    Horiguchi, Susumu
    21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2006, : 353 - +
  • [32] AN OPTIMAL DOMAIN-BASED RECONFIGURATION ALGORITHM FOR WSI PROCESSOR ARRAYS
    KIM, JH
    RHEE, PK
    HA, DS
    MICROPROCESSING AND MICROPROGRAMMING, 1992, 33 (05): : 261 - 278
  • [33] Reconfiguration algorithm for degradable processor arrays based on row and column rerouting
    Fukushi, M
    Horiguchi, S
    19TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2004, : 496 - 504
  • [34] A resource-efficient encryption algorithm for multimedia big data
    Shadi Aljawarneh
    Muneer Bani Yassein
    We’am Adel Talafha
    Multimedia Tools and Applications, 2017, 76 : 22703 - 22724
  • [35] Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays
    Qian, Junyan
    Ding, Hao
    Xiao, Hanpeng
    Zhou, Zhide
    Zhao, Lingzhong
    Zhai, Zhongyi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (01) : 267 - 271
  • [36] Design of an efficient VLSI architecture for 2-D discrete wavelet transforms
    Yu, C
    Chen, SJ
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1999, 45 (01) : 135 - 140
  • [37] An Efficient VLSI Architecture For 2-D Dual-Mode SMDWT
    Hsia, Chih-Hsien
    Chiang, Jen-Shiun
    Chang, Shih-Hao
    2013 10TH IEEE INTERNATIONAL CONFERENCE ON NETWORKING, SENSING AND CONTROL (ICNSC), 2013, : 775 - 779
  • [38] An efficient line based VLSI architecture for 2-D lifting DWT
    Jung, GC
    Jin, DY
    Park, SM
    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 249 - 252
  • [39] Efficient Architectures for VLSI Implementation of 2-D Discrete Hadamard Transform
    Mohanty, Basant Kumar
    Meher, Pramod Kumar
    Singhal, Subodh Kumar
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1480 - 1483
  • [40] Efficient VLSI architecture for 2-D inverse discrete wavelet transforms
    Yu, C
    Chen, SJ
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 524 - 527