MODELING OF LITHOGRAPHY RELATED YIELD LOSSES FOR CAD OF VLSI CIRCUITS.

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作者：
Maly, Wojciech [1 ]
机构：
[1] Carnegie-Mellon Univ, Dep of, Electrical & Computer, Engineering, Pittsburgh, PA, USA, Carnegie-Mellon Univ, Dep of Electrical & Computer Engineering, Pittsburgh, PA, USA
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| 1600年 / CAD-4期
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摘要：
INTEGRATED CIRCUITS, VLSI
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