A hybrid bionic optimization algorithm for test access mechanism of system-on-chip

被引:0
|
作者
Gu, Juan [1 ]
Cui, Xiao-Le [2 ]
Yin, Liang [2 ]
Cheng, Wei [2 ]
机构
[1] College of Physics Science and Technology, Shenzhen University, Shenzhen 518060, China
[2] Key Lab of Integrated Microsystems, Shenzhen Graduate School, Peking University, Shenzhen 518055, China
来源
Shenzhen Daxue Xuebao (Ligong Ban)/Journal of Shenzhen University Science and Engineering | 2010年 / 27卷 / 04期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:428 / 432
相关论文
共 50 条
  • [21] Preemptive system-on-chip test scheduling
    Larsson, E
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2004, E87D (03): : 620 - 629
  • [22] An integrated system-on-chip test framework
    Larsson, E
    Peng, Z
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 138 - 144
  • [23] Optimal system-on-chip test scheduling
    Larsson, E
    Fujiwara, H
    ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 306 - 311
  • [24] Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm
    Chandrasekaran, Gokul
    Kumar, Neelam Sanjeev
    Karthikeyan, P. R.
    Vanchinathan, K.
    Priyadarshi, Neeraj
    Twala, Bhekisipho
    IEEE ACCESS, 2022, 10 : 126199 - 126216
  • [25] Design and optimization of test solutions for core-based system-on-chip benchmark circuits using genetic algorithm
    Sakthivel, P.
    Narayanasamy, P.
    WORLD CONGRESS ON ENGINEERING 2007, VOLS 1 AND 2, 2007, : 249 - +
  • [26] An approach to the design of optimal test scheduling for system-on-chip based on genetic algorithm
    Sakthivel, P.
    Narayanasamy, P.
    INNOVATIONS AND ADVANCED TECHNIQUES IN COMPUTER AND INFORMATION SCIENCES AND ENGINEERING, 2007, : 25 - +
  • [27] A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH POWER AND PRECEDENCE CONSTRAINTS
    Harmanani, Haidar M.
    Salamy, Hassan A.
    INTERNATIONAL JOURNAL OF COMPUTATIONAL INTELLIGENCE AND APPLICATIONS, 2006, 6 (04) : 511 - 530
  • [28] Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms
    Chandrasekaran, Gokul
    Karthikeyan, P. R.
    Kumar, Neelam Sanjeev
    Kumarasamy, Vanchinathan
    JOURNAL OF INTELLIGENT & FUZZY SYSTEMS, 2021, 40 (03) : 4905 - 4917
  • [29] Test Vector Compression Technique in System-on-Chip
    Biswas, Satyendra N.
    Das, Sunil R.
    Assaf, Mansour H.
    Hossain, Altaf
    I2MTC: 2009 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-3, 2009, : 1099 - +
  • [30] A note on system-on-chip test scheduling formulation
    Koranne, S
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2004, 20 (03): : 309 - 313