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- [21] Performance Enhancement of a Hybrid 1-bit Full Adder Circuit PROCEEDINGS OF THE FIRST IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, INTELLIGENT CONTROL AND ENERGY SYSTEMS (ICPEICES 2016), 2016,
- [22] A Novel Power Efficient N-MOS Based 1-Bit Full Adder 2016 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING AND COMMUNICATIONS (MICROCOM), 2016,
- [23] Implementation of Low Power 1-bit Hybrid Full Adder using 22 nm CMOS Technology 2020 6TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATION SYSTEMS (ICACCS), 2020, : 1215 - 1217
- [24] Power optimization of 1-bit CMOS full adder using gate resizing and voltage scaling technique CCCT 2003, VOL 4, PROCEEDINGS: COMPUTER, COMMUNICATION AND CONTROL TECHNOLOGIES: I, 2003, : 213 - 217
- [26] Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell Wireless Personal Communications, 2023, 129 : 1097 - 1111
- [27] Design and Implementation of a 1-bit FinFET Full Adder Cell for ALU in Subthreshold Region 2014 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS (ICSE), 2014, : 44 - 47
- [28] A Competent Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2013, : 1519 - 1523
- [29] Area and Power Efficient Carry Select Adder using 8T Full Adder 2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2015, : 969 - 973
- [30] Low Power Noise Tolerant Domino 1-Bit Full Adder PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON ADVANCES IN ENERGY CONVERSION TECHNOLOGIES (ICAECT): INTELLIGENT ENERGY MANAGEMENT: TECHNOLOGIES AND CHALLENGES, 2014, : 125 - 129