共 50 条
- [41] Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology 2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE), 2017, : 427 - 432
- [42] Parametric analysis of a hybrid 1-bit full adder in UDSM and CNTFET Technology 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4267 - 4272
- [43] Design of Fast and Efficient 1-bit Full Adder and its Performance Analysis 2014 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2014, : 1275 - 1279
- [45] New High Performance 1-Bit Full Adder Using Domino Logic 2014 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS, 2014, : 961 - 965
- [46] Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder ADCAIJ-ADVANCES IN DISTRIBUTED COMPUTING AND ARTIFICIAL INTELLIGENCE JOURNAL, 2022, 11 (04): : 475 - 488
- [48] A novel CMOS full adder 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 303 - +
- [49] A Low-Power High-Speed 16T 1-Bit Hybrid Full Adder 2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE), 2017, : 348 - 352
- [50] A Novel Ultra-Low Power and PDP 8T Full Adder Design Using Bias Voltage 2017 2ND INTERNATIONAL CONFERENCE FOR CONVERGENCE IN TECHNOLOGY (I2CT), 2017, : 1069 - 1073