Area-efficient high-speed VLSI design of the RS(255, 239) decoder

被引:0
|
作者
School of Microelectronic, Xidian Univ., Xi'an 710071, China [1 ]
不详 [2 ]
机构
关键词
12;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:116 / 120
相关论文
共 50 条
  • [1] High-Speed RS(255, 239) Decoder Based on LCC Decoding
    F. García-Herrero
    J. Valls
    P. K. Meher
    [J]. Circuits, Systems, and Signal Processing, 2011, 30 : 1643 - 1669
  • [2] High-Speed RS(255,239) Decoder Based on LCC Decoding
    Garcia-Herrero, F.
    Valls, J.
    Meher, P. K.
    [J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2011, 30 (06) : 1643 - 1669
  • [3] VLSI design of a high-speed and area-efficient JPEG2000 encoder
    Mei, Kuizhi
    Zheng, Nanning
    Huang, Chang
    Liu, Yuehu
    Zeng, Qiang
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2007, 17 (08) : 1065 - 1078
  • [4] VLSI design, and implementation of high-speed RS(204,188) decoder
    You, YX
    Wang, JX
    Lai, FC
    Ye, YZ
    [J]. 2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4, 2002, : 82 - 86
  • [5] VLSI design of pipeline RS(255, 223) decoder
    [J]. 2000, Sci Press (37):
  • [6] A VLSI design of a pipelining and area-efficient Reed-solomon decoder
    Wang, Wei-min
    Bi, Du-yan
    Du, Xing-min
    Ma, Lin-hua
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2007, E90D (08) : 1301 - 1303
  • [7] Area-efficient VLSI design of Reed-Solomon decoder for HDTV
    Information Engineering School, Beijing University of Science and Technology, Beijing 100083, China
    [J]. Jisuanji Gongcheng, 2006, 16 (11-13+28):
  • [8] An area-efficient high-speed reed-solomon decoder in 0.25μm CMOS
    Strollo, AGM
    Petra, N
    De Caro, D
    Napoli, E
    [J]. ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, : 479 - 482
  • [9] VLSI implementation of area-efficient List Sphere Decoder
    Lee, Seungbeom
    Lee, Jin
    Park, Sin-Chong
    [J]. 2006 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2006, : 1465 - +
  • [10] High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
    Panda, Amit Kumar
    Palisetty, Rakesh
    Ray, Kailash Chandra
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (11) : 3944 - 3953