Area-efficient high-speed VLSI design of the RS(255, 239) decoder

被引：0
|
作者：
School of Microelectronic, Xidian Univ., Xi'an 710071, China [1 ]
不详 [2 ]
机构：
来源：
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2008年 / 35卷 / 01期
关键词：
12;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：116 / 120
相关论文
共 50 条
  • [11] Area-Efficient Pipelined VLSI Architecture for Polar Decoder
    Tan, Weihang
    Wang, Antian
    Xu, Yunhao
    Lao, Yingjie
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 352 - 357
  • [12] VLSI implementation of area-efficient list sphere decoder
    Lee, Seungbeom
    Lee, Jin
    Seo, Sang-ho
    Park, Sin-Chong
    2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2, 2006, : 557 - +
  • [13] AN AREA-EFFICIENT PATH MEMORY STRUCTURE FOR VLSI IMPLEMENTATION OF HIGH-SPEED VITERBI DECODERS
    PAASKE, E
    PEDERSEN, S
    SPARSO, J
    INTEGRATION-THE VLSI JOURNAL, 1991, 12 (01) : 79 - 91
  • [14] HIGH-SPEED AREA-EFFICIENT VERSATILE REED-SOLOMON DECODER DESIGN FOR MULTI-MODE APPLICATIONS
    Yuan, Bo
    Li, Li
    Wang, Zhongfeng
    SIPS: 2009 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, 2009, : 179 - +
  • [15] VLSI design and implementation of a high-speed Viterbi decoder
    Li, Qing
    Deng, Yunsong
    Zeng, Xiaoyang
    Gu, Yehua
    Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2007, 44 (12): : 2143 - 2148
  • [16] VLSI design and implementation of high-speed Viterbi decoder
    You, YX
    Wang, JX
    Lai, FC
    Ye, YZ
    2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4, 2002, : 64 - 68
  • [17] Area-efficient high-speed carry chain
    Amin, A. A.
    ELECTRONICS LETTERS, 2007, 43 (23) : 1258 - 1260
  • [18] Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
    Wielage, Paul
    Marinissen, Erik Jan
    Altheimer, Michel
    Wouters, Clemens
    2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2007, : 853 - +
  • [19] An area-efficient VLSI architecture for Reed-Solomon decoder
    Guo, YF
    Li, ZC
    Wang, Q
    INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2005, VOLS 1 AND 2, PROCEEDINGS, 2005, : 1154 - 1158
  • [20] A VLSI design of a high-speed Reed-Solomon decoder
    Lee, HH
    14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 316 - 320
12345