共 50 条
- [41] A novel CMOS full adder 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 303 - +
- [43] Progress in reversible processor design: A novel methodology for reversible carry look-ahead adder Thapliyal, H. (hthapliy@cse.usf.edu), 1600, Springer Verlag (7420):
- [44] Design of Optimized Reversible Binary Adder/Subtractor and BCD Adder 2014 INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING AND INFORMATICS (IC3I), 2014, : 774 - 779
- [45] A New Reversible Design of BCD Adder 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1180 - 1183
- [46] Optimal Design of Full Adder Circuit using Particle Swarm Optimization Algorithm 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 2023 - 2028
- [47] A General Method of Constructing the Reversible Full-adder 2010 THIRD INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION TECHNOLOGY AND SECURITY INFORMATICS (IITSI 2010), 2010, : 109 - 113
- [48] A reversible full adder using adiabatic superconductor logic SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 2019, 32 (03):
- [49] Optimized design and performance analysis of novel comparator and full adder in nanoscale COGENT ENGINEERING, 2016, 3 (01):
- [50] Reversible Full/Half Adder With Optimum Power Dissipation PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16), 2016,