OPTIMIZATION OF 8T SRAM BIT-CELL DESIGN

被引：0

作者：

Wu, Luping ^{[1
]}

Wang, Chunhsiung ^{[1
]}

Mo, Hongxiang ^{[1
]}

机构：

[1] HFC Semicond, SRAM Dept, Hangzhou, Peoples R China

来源：

CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC | 2024年

关键词：

SRAM; 8T bit-cell design; write margin; model simulation;

D O I：

10.1109/CSTIC61820.2024.10532111

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper, the simulation result reveals that write failure exists on the original two-port bitcell and with the optimized design, the write ability is improved by >66% over the normal 6T SRAM bitcell. A composite failure mode for 8T SRAM write operation was proposed according to the simulation data. Besides, the advantage of two-port SRAM, that the separated read port has no impact on write margin (WRM), has been clarified by decoupled circuit simulation for the first time. Simulations are performed using cadence virtuoso tool.

引用

页数：3

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