Power Optimizaton in 8T SRAM Cell

被引：0

作者：

Dnyaneshwar, Kakde ^{[1
]}

Birgale, L. V. ^{[1
]}

机构：

[1] SGGSI & T, Dept Elect & Telecommun, Vishnupuri, Nanded, India

来源：

2016 INTERNATIONAL CONFERENCE ON COMPUTING COMMUNICATION CONTROL AND AUTOMATION (ICCUBEA) | 2016年

关键词：

Eight transistor (8T); Drain induced barrier lowering (DIBL); Static random access memory (SRAM);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Transistor scaling has provided high-density VLSI circuits with increased performance. The performance is increased at the cost of increased power density. Therefore demand for power sensitive design techniques is increased significantly. Several process and circuit level techniques have been proposed to control the power (leakage) dissipation. In this paper, we propose circuit level techniques to reduce power dissipation effectively for 8T SRAM cell in 90nm technology using Cadence tools.

引用

页数：4

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