A novel 8T SRAM with improved cell density

Low voltage and high-density SRAM memory creates new challenges such as stability and sense margin. Conventional decoupled 8T SRAM cell has improved read stability but small sense margin and high leakage power which makes it unsuitable for small supply and high density memories. Proposed decoupled 8T SRAM cell improves sense margin during reading by reducing data leakage current of neighboring SRAM cells which are OFF and write stability by using negative bit line scheme. It is evident from the simulation results that proposed 8T SRAM minimizes leakage current by 49.2% when compared to conventional 8T SRAM cell. It gives stable read for 20.2K cells per bitline at 0.8V at room temperature but conventional 8T SRAM can give successful read for 5.83K cells.